Semiconductor device manufacturing method

ABSTRACT

A method of manufacturing a semiconductor device for realizing a semiconductor device which is suitable for enhancing the operating speed thereof and which is high in quality and reliability is provided.  
     The method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device including a barrier film ( 7 ) having a copper diffusion preventive function and formed on a copper-containing metallic wire ( 9 ), the method including the steps of: conducting electroplating by use of an electroplating liquid containing a catalyst metal ( 10 ) added thereto so as thereby to form the metallic wiring ( 2 ) containing the catalyst metal ( 10 ); and conducting electroless plating by use of the catalyst metal ( 10 ) exposed at the surface of the metallic wiring ( 2 ) as a catalyst so as thereby to form the barrier film ( 7 ) having the copper diffusion preventive function on the metallic wiring ( 2 ).

TECHNICAL FIELD

The present invention relates to a method of manufacturing asemiconductor device including a metallic wiring containing copper, andparticularly to a method of manufacturing a semiconductor device inwhich diffusion of copper into an inter-layer insulating film or thelike is prevented.

BACKGROUND ART

Conventionally, aluminum-based alloys are used as a material of a minutewiring of a high-density integrated circuit formed on a semiconductorwafer. For enhancing the operating speed of a semiconductor device,however, it is necessary to use a material lower in resistivity thanaluminum-based alloys as the wiring material, and copper, silver and thelike are preferable for use as such a low-resistivity material.Particularly, copper is expected as a next-generation material becauseit has a low resistivity of 1.8 μΩcm, it is therefore advantageous forenhancing the operating speed of a semiconductor device, and it ishigher in electro-migration resistance than aluminum-based alloys byabout one order.

In formation of a wiring by use of copper, generally, the so-calledDamascene process is used because dry etching of copper is difficult tocarry out. The process includes the steps of preliminarily forming agroove in an inter-layer insulating film formed, for example, of siliconoxide, filling the groove with a wiring material (copper), and removingthe excess wiring material by chemical mechanical polishing (hereinafterreferred to as CMP), thereby forming a wiring. Further, there has beenknown the dual Damascene process including the steps of formingconnection holes (via holes) and a wiring groove (trench), thencollectively filling these with a wiring material, and removing theexcess wiring material by CMP.

Meanwhile, the copper wiring is generally used in the form of amulti-layer structure. In this case, for the purpose of preventing thediffusion of copper into the inter-layer insulating film, a barrier filmconsisting of silicon nitride, silicon carbide or the like is formedbefore the formation of the wiring.

However, since the barrier film is absent on the surface of the copperwiring immediately after the CMP, the barrier film for functioning as acopper diffusion preventive layer is formed before the formation of theupper-layer wiring. In this case, since copper is easily oxidized in anoxygen-containing atmosphere even at a low temperature of around 150°C., a silicon nitride film (SiN) a silicon carbide film (SiC) or thelike is ordinarily used as the barrier layer.

It should be noted here that silicon nitride (SiN) and silicon carbide(SiC) are higher in relative dielectric constant than silicon oxide(SiO₂), which leads to the problems that the effective dielectricconstant of the semiconductor device including the copper wiring will behigh, the semiconductor will be high in RC delay (delay of the wiringdue to resistance and capacitance), and the electro-migration resistanceat the interface between the SiN or SiC constituting the barrier filmand copper will be weak.

In view of the above problems, formation of a film of CoWP on thesurface of the copper wiring after the CMP as a material which isexcellent in prevention of copper diffusion, improvement of RC delay,and electro-migration resistance has been proposed by U.S. Pat. No.5,695,810 (USE OF COBALT TUNGSTEN PHOSPHITE AS A BARRIER MATERIAL FORCOPPER METALLIZATION). Furthermore, CoWP has the characteristic featurethat a film thereof can be selectively formed only on the copper wiringby electroless plating.

A conventional semiconductor device using CoWP as the barrier film isshown in FIG. 21. The semiconductor device includes a copper-containingmetallic wiring, on which is formed a barrier film composed of CoWP andhaving a copper diffusion preventive function. The semiconductor devicehas a constitution in which lower-layer wirings 102 a and 102 b as thecopper-containing metallic wirings (hereinafter referred to as Cuwirings) are used to fill grooves provided in an insulating layer 103 a,on a substrate 101 preliminarily provided with devices (not shown) suchas transistors. The insulating layer 103 a is formed, for example, ofSiOC, and a barrier metal film 104 a formed, for example, of TaN isformed between the lower-layer wirings 102 a, 102 b and the insulatinglayer 103 a. In addition, an etch stopper layer 105 formed of SiC, forexample, is formed between the substrate 101 and the insulating layer103 a, for preventing the diffusion of Cu from the lower-layer wirings102 a and 102 b into the substrate 101. Besides, an insulating film 103b is provided on the lower-layer wirings 102 a and 102 b and theinsulating layer 103 a, with an SiN film for copper diffusion preventiontherebetween. The insulating film 103 b is formed of SiO₂, for example.

Furthermore, an insulating film 103 c is formed on the insulating film103 b, with an SiN film for copper diffusion prevention therebetween,and upper-layer wirings 106 a and 106 b as copper-containing metallicwirings are formed in grooves provided in the insulating layer 103 b andthe insulating layer 103 c, with a barrier metal film 104 b consisting,for example, of TaN therebetween. A barrier film 108 consisting of CoWPand having a copper diffusion preventing function is formed on theupper-layer wirings 106 a and 106 b, i.e., on the surfaces not coveredwith the barrier metal film 104 b, i.e., the top surfaces in FIG. 21, ofthe upper-layer wirings 106 a and 106 b, with a palladium (Pd)replacement layer 107 therebetween.

To manufacture the above-mentioned semiconductor device, electrolessplating with CoWP is applied onto the copper wiring, to form the barrierlayer. Now, the method and principle of forming a film of CoWP on thecopper wiring by electroless plating will be described in brief. Inorder to selectively forming the film of CoWP on the copper wiring bythe electroless plating method, a catalyst layer for startingelectroless plating is needed. Copper is low in catalytic activity, and,therefore, it does not function as a sufficient catalyst for depositionof CoWP. In general, therefore, a method in which a catalytic metallayer of palladium (Pd) or the like is preliminarily formed on thecopper surface by replacement plating.

The replacement plating utilizes the differences in ionization tendencybetween different metals. Since Cu is electrochemically baser than Pd,when Cu is immersed in an HCl solution of PdCl₂, for example, electronslibrated attendant on the dissolution of Cu are transferred onto theions of Pd which is a noble metal in the solution, resulting in theformation of a film of Pd on the surface of Cu which is the baser metal.Since the Pd replacement does not occur on the surfaces of insulatingfilms which necessarily are not metallic, the catalytically active layeris formed only on Cu. Subsequently, an electroless plating reactionstarts only on the Cu wiring, with the Pd layer as a catalyst, resultingin the formation of a barrier metal layer formed of CoWP.

The above-mentioned method, however, has the problem that the Cu wiringis damaged by etching when the catalytically active layer is formed onthe Cu surface by the Pd replacement plating. Particularly, holes arelocally formed in Cu along Cu grains, and, where etching is vigorous,the Cu wiring may be damaged to such an extent as to cause linebreakage. As a result, the resistance of the Cu wiring is raised by asmuch as 30%, for example, where the Cu wiring is severely damaged.Furthermore, it is difficult to fill the holes, generated between the Cugrains, by the formation of the CoWP film. As a result, even after theformation of the CoWP, voids would be left in the Cu wiring, and theelectro-migration resistance would be rapidly worsened starting from thevoids.

The present invention has been devised in consideration of theabove-mentioned circumstances of the prior art. Accordingly, it is anobject of the present invention to provide a method of manufacturing asemiconductor device for realizing a semiconductor device which issuitable for enhancing the operating speed thereof and is high inquality and reliability.

DISCLOSURE OF INVENTION

In order to attain the above object, according to the present invention,there is provided a method of manufacturing a semiconductor deviceincluding a barrier film having a copper diffusion preventive functionand formed on a metallic wiring, the method including the steps of:conducting electroplating by use of an electroplating liquid containinga catalyst metal added thereto so as thereby to form a metallic wiringcontaining the catalyst metal; and conducting electroless plating by useof the catalyst metal exposed at the surface of the metallic wiring as acatalyst so as thereby to form the barrier film having the copperdiffusion preventive function on the metallic wiring.

Conventionally, in order to form a barrier film on a copper-containingmetallic wire by an electroless plating method, it has been necessary tosubject the surface of the metallic wiring layer to a catalyticallyactivating treatment using Pd or the like which is a highly catalyticmetal. Specifically, it is necessary, for example, to subject thesurface of the copper-containing metallic wiring to Pd replacementplating, thereby replacing copper by Pd to form a catalytically activelayer, and thereafter to conduct electroless plating by using Pd in thecatalytically active layer as nuclei of catalyst.

In the method of manufacturing a semiconductor device according to thepresent invention, however, in forming the copper-containing metallicwiring, the catalyst metal is preliminarily contained in the metallicwiring, and electroless plating is conducted using the catalyst metalexposed at the surface of the metallic wiring, of the catalyst metalcontained in the metallic wiring, as nuclei of catalyst to thereby formthe barrier film having the copper diffusion preventive function on themetallic wiring.

To be more specific, in the method of manufacturing a semiconductordevice according to the present invention, the catalyst metal ispreliminarily added to the electroplating liquid for electroplating, informing the copper-containing metallic wiring by electroplating. Thecatalyst metal functions as a catalyst for starting an electrolessplating reaction, in forming the barrier film. Then, electroplating isconducted using the electroplating liquid containing the catalyst metaladded thereto, whereby the metallic wiring containing the catalyst metalcan be formed. That is, it is possible to form a metallic wiring inwhich the catalyst metal is dispersed inside the metallic wiring and atthe surface of the metallic wiring.

Then, removal of unrequired portions and a planarizing treatment areconducted as required, and electroless plating for forming the barrierfilm by using as a catalyst the catalyst metal exposed at the surface ofthe metallic wiring, upon which an electroless plating reaction beginswith the catalyst metal as a catalyst, and the electroless platingreaction continues due to an autocatalytic action, whereby the barrierfilm is formed on the metallic wiring.

Here, the catalyst metal is exposed only at the surface of the metallicwiring, and the electroless plating proceeds only where the catalystmetal is present. Therefore, the barrier film can be selectively formedonly on the metallic wiring.

In the above-described method, the metallic wiring is formed by theelectroplating using the electroplating liquid containing the catalystmetal preliminarily added thereto, whereby the catalyst metal forfunctioning as the catalyst in electroless plating is dispersed insidethe metallic wiring and at the surface of the metallic wiring. Thismakes it possible to obtain the same effect as that in the case ofapplying the catalytically activating treatment in the conventionalmanufacturing method.

In the present invention, therefore, the catalytically activatingtreatment step indispensable to the conventional manufacturing method isunnecessitated, the barrier film can be efficiently formed by simplifiedmanufacturing steps, and it is possible to manufacture at low cost ahigh-quality semiconductor device in which diffusion of copper atomsinto an inter-layer insulating film is securely prevented.

Besides, in the method of manufacturing a semiconductor device accordingto the present invention, the metallic wiring itself will not be etchedbecause the catalytically activating step is not conducted, as describedabove. Specifically, the metallic wiring is free of generation of holesin the metallic wiring due to etching, and is free of damages due toetching, such as generation of line breakage. Therefore, it is possibleto manufacture a high-quality semiconductor device while obviating theproblems which might cause malfunctions of the semiconductor device,such as a rise in the wiring resistance and a worsening ofelectro-migration resistance, arising from etching of the metallicwiring.

Furthermore, in the method of manufacturing a semiconductor deviceaccording to the present invention, the catalytically activating step isnot carried out, and, therefore, the adsorption or remaining of thecatalyst metal onto the inter-layer insulating film as in theconventional manufacturing method is obviated. As a result, the barrierfilm is not formed on the inter-layer insulating film, and, therefore,it is possible to enhance the selectivity of film formation at the timeof forming the barrier film and to manufacture a high-qualitysemiconductor device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a vertical sectional view showing one example of theconfiguration of a semiconductor device produced by applying the presentinvention.

FIG. 2 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 3 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 4 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 5 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 6 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 7 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 8 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 9 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 10 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device according to the present invention.

FIG. 11 is a vertical sectional view showing the condition where alower-layer wiring has been formed by applying the present invention.

FIG. 12 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 13 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 14 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 15 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 16 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 17 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 18 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 19 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 20 is a vertical sectional view for illustrating the method ofmanufacturing a semiconductor device in the case where the presentinvention is applied to the dual Damascene process.

FIG. 21 is a vertical sectional view showing one example of theconfiguration of a semiconductor device according to the related art.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, the method of manufacturing a semiconductor device according to thepresent invention will be described in detail below referring to thedrawings. The present invention is not limited to the followingdescription, and various modifications are possible within the gist ofthe invention. First, the case where the present invention is applied toa monolayer wiring will be described. In the following drawings, thecontraction scale may differ from the actual one, for convenience ofdescription.

FIG. 1 is a sectional view of an essential part of a semiconductordevice produced by applying the present invention. The semiconductordevice includes a copper-containing metallic wire, on which is formed abarrier film having a copper diffusion preventive function. Thesemiconductor device has a configuration in which the copper-containingmetallic wire (hereinafter referred to as Cu wiring) 2 is filling agroove provided in an inter-layer insulating film 3, on a substrate 1preliminarily provided with devices (not shown) such as transistors.

The inter-layer insulating film 3 is composed, for example, of SiOC,SiO₂, SiLK, FLARE, a fluorine-added silicon oxide film (FSG) or otherlow-dielectric-constant insulating film. Between the Cu wiring 2 and theinter-layer insulating film 3 are formed a barrier metal film 4 having acopper diffusion preventive function, and a Cu seed layer 5 which is tobe a conductive layer in forming a film of Cu by electroplating in a Cufilling step. The barrier metal film 4 is composed, for example, of TaN,Ta, Ti, TiN, W, WXN, or a laminated film thereof.

In addition, between the substrate 1 and the inter-layer insulating film3 is formed an etch stopper layer 6 composed, for example, SiN, SiC, orthe like.

Besides, in the semiconductor device, a barrier film 7 having a copperdiffusion preventive function is formed on the Cu wiring 2, i.e., onthat surface of the Cu wiring 2 which is not covered with the barriermetal film 4, i.e., on the top surface in FIG. 1. Here, the barrier film7 is constituted of cobalt tungsten phosphite (CoWP) film formed on theCu wiring. With the barrier film 7 constituted of cobalt tungstenphosphite (CoWP), in the semiconductor device, the barrier film 7consisting of cobalt tungsten phosphite (CoWP) functions sufficiently asa copper diffusion preventive film, whereby diffusion of copper into theinter-layer insulating film is securely prevented.

In addition, with the barrier film 7 constituted of cobalt tungstenphosphite (CoWP), in the semiconductor device, the problem thatelectro-migration resistance is weak at the interface between the copperdiffusion preventive film and copper and the problem that RC delay islarge due to the high dielectric constant of the copper diffusionpreventive film itself, which would occur where SiN or the like is usedas the material of the barrier film 7, namely, the copper diffusionpreventive film, are obviated. Namely, by using a film of cobalttungsten phosphite (CoWP) as the barrier film 7, there is realized asemiconductor device which is excellent in copper diffusion preventiveproperty, which has an excellent electro-migration resistance and inwhich RC delay is suppressed.

The semiconductor device as above can be produced as follows. First, asshown in FIG. 2, a material such as SiC and SiN is deposited on thesubstrate 1 by a CVD (Chemical Vapor Deposition) process, to form theetch stopper layer 6. Specifically, for example, a CVD process isconducted using a mixture gas of monosilane (SiH₄), NH₃ and N₂ as asource gas, to form a film of SiN in a film thickness of 50 nm.

Next, as shown in FIG. 3, in continuation with the formation of the etchstopper layer 6, the inter-layer insulating film 3 consisting of SiO₂ isformed on the whole surface of the etch stopper layer 6 by a CVD processusing, for example, a mixture gas of tetraethoxysilane (TEOS) and O₂ asa raw material gas. The formation of the inter-layer insulating film 3can be conducted in continuity with the formation of the etch stopper 6in the preceding step in the same chamber. Besides, the material of theinter-layer insulating film 3 is not limited to SiO₂ but may be a knownoxide such as SiOC or may be an organic material such as alow-dielectric-constant material.

Subsequently, as shown in FIG. 4, a groove 8 for forming a wiring ispatterned in the inter-layer insulating film 3 by photolithography anddry etching. For example, the etching of the inter-layer insulating film3 can be carried out under the following etching conditions. <EtchingConditions for Inter-layer Insulating Film 3> Gas used: CHF₃/CF₄/Ar =30/60/800 sccm Pressure: 200 Pa Substrate temperature: 25° C.

Next, as shown in FIG. 5, the barrier metal film 4 consisting, forexample, TaN for preventing the diffusion of Cu into the inter-layerinsulating film 3 is formed by a PVD (Physical Vapor Deposition)process. The material of the barrier metal film 4 is not limited to TaN;a material excellent in barrier property against Cu, such as Ta, Ti,TiN, W, WN, or a laminated film thereof and the like can be used as thematerial of the barrier metal film 4.

Subsequently, as shown in FIG. 6, the Cu seed layer 5 is formed on thebarrier metal film 4 by a PVD process. The Cu seed layer 5 is to be aconductive layer in forming a film of Cu by electroplating in thesubsequent Cu filling step. The formation of the barrier metal film 4and the Cu seed layer 5 may not necessarily be conducted by the PVDprocess but may be conducted by a CVD process.

The film thicknesses depend on design rules. It is preferable, however,that the film thickness of the barrier metal film 4 is not more than 50nm, and the film thickness of the Cu seed layer 5 is not more than 200nm. Therefore, the barrier metal film 4 consisting of TaN, for example,may be formed in a film thickness of 20 nm, and the Cu seed layer 5 maybe formed on the barrier metal film 4 in a film thickness of 150 nm. Oneexample of a set of PVD film formation conditions for the barrier metalfilm 4 in this instance is given below. <PVD Film Formation Conditionsfor Barrier Metal Film 4> DC power: 1 kW Process gas: Ar = 50 sccm ACwafer bias power: 350 W

Besides, one example of a set of PVD film formation conditions for theCu seed layer 5 is given below. <PVD Film Formation Conditions for CuSeed Layer 5> DC power: 12 kW Pressure: 0.2 Pa Film formationtemperature: 100° C.

Next, as shown in FIG. 7, a film of Cu 9 is formed by Cu electroplating,to fill the groove 8 with Cu 9. In this case, Pd as a catalyst metal 10a is preliminarily added to a Cu electroplating liquid for use in Cuelectroplating. The catalyst metal 10 a is to be a catalyst for startingan electroless plating reaction in forming the barrier film 7 which willbe described later. Then, the film of Cu 9 is formed by Cuelectroplating using the Cu electroplating liquid containing thecatalyst metal 10 a such as Pd added thereto, in the manner of fillingthe groove 8 with Cu 9, whereby the Cu wiring 2 containing the catalystmetal 10 a can be formed. Specifically, it is possible to form the Cuwiring 2 such that the catalyst metal 10 a is dispersed at random insidethe Cu wiring 2 and at the surface of the Cu wiring 2.

In the conventional method of manufacturing a semiconductor device, inorder to form the barrier film 7 on the Cu wiring 2, the surface of theCu wiring 2 must be subjected to a catalytically activating treatmentusing Pd or the like which is a highly catalytic metal. Specifically, itis necessary, for example, to replace the surface of the Cu wiring 2with Pd by Pd replacement plating, thereby forming a catalyticallyactive layer on the surface of the Cu wiring 2, and then to conductingelectroless plating by use of Pd of the catalytically active layer asnuclei of catalyst.

On the other hand, in the method of manufacturing a semiconductor deviceaccording to the present invention, the Cu wiring 2 containing thecatalyst metal 10 a can be formed by conducting Cu electroplating whileusing the Cu electroplating liquid containing the catalyst metal 10 apreliminarily added thereto, as described above. Namely, the catalystmetal 10 a as a catalyst for starting an electroless plating reactioncan be dispersed inside the Cu wiring 2 and at the surface of the Cuwiring 2.

This makes it possible to obtain the same effect as that in the case ofapplying the catalytically activating treatment in the conventionalmanufacturing method, so that the catalytically activating treatmentindispensable to the conventional manufacturing method isunnecessitated. In the method of manufacturing a semiconductor deviceaccording to the present invention, therefore, it is possible toefficiently form the barrier film 7 by simplified manufacturing steps,and to manufacture at low cost a high-quality semiconductor device inwhich the diffusion of copper atoms into the inter-layer insulating filmis securely prevented.

Besides, in the method of manufacturing a semiconductor device accordingto the present invention, the Cu wiring 2 is not etched at the time offorming the barrier layer 7, since the catalytically activating step isnot performed. In addition, in the method of manufacturing asemiconductor device according to the present invention, the absence ofthe catalytically activating step ensures that the Cu wiring 2 is freeof generation of holes in the Cu wiring 2 by etching and is free ofdamage due to etching, such as generation of line breakage. Therefore, arise in wiring resistance, a worsening of electro-migration resistance,and the like, due to etching of the Cu wiring 2, are obviated.Accordingly, it is possible to manufacture a high-quality semiconductordevice in which malfunctions of the semiconductor device due to etchingof the Cu wiring 2 will not occur.

In the method of manufacturing a semiconductor device according to thepresent invention, furthermore, the catalytically activating step is notcarried out, and, therefore, the adsorption or remaining of the catalystmetal onto the inter-layer insulating film 3, as seen in theconventional manufacturing method, is obviated. As a result, formationof the barrier layer 7 on the inter-layer insulating film 3 is obviated,making it possible to enhance the selectivity of film formation informing the barrier film 7 which will be described later. This isbecause electroless plating proceeds only where the catalyst metal 10 ispresent, and the catalyst metal 10 a is selectively disposed only on theCu wiring 2 in the method of manufacturing a semiconductor deviceaccording to the present invention.

In addition, since a copper sulfate-based electroplating liquid isgenerally used for Cu electroplating, where Pd, for example is used asthe catalyst metal, the method for adding the catalyst metalabove-mentioned preferably consists in adding palladium sulfate to theCu electroplating liquid. In the case where palladium sulfate is simplyadded to the Cu electroplating liquid, however, hydroxide of Pd isproduced by hydrolysis in the Cu electroplating liquid, and thehydroxide migrates in the Cu electroplating liquid, leading todiscoloration of the plating liquid and rendering the electroplatinginstable.

In view of this problem, in the present invention it is preferable toadd the catalyst metal in a complexed form to the Cu electroplatingliquid. Specifically, in the case where Pd, for example, is added as thecatalyst metal, Pd is preferably complexed with citric acid or the like,before being added to the Cu electroplating liquid. With the thuscomplexed Pd added to the Cu electroplating liquid, generation ofhydroxide of Pd due to hydrolysis in the Cu electroplating liquid isobviated, so that there is no possibility of migration of the hydroxidein the Cu electroplating. Therefore, discoloration of the plating liquidand instability of electroplating, due to the hydroxide of Pd, areprevented, and it is possible to achieve a stable high-quality Cuelectroplating.

In addition, the catalyst metal to be added to the Cu electroplatingliquid is not limited to Pd; gold (Au), platinum (Pt), silver (Ag),rhodium (Rh), cobalt (Co), nickel (Ni) and the like can be used as thecatalyst metal. Also in the case of adding any of these metals as thecatalyst metal to the Cu electroplating liquid, it is preferable tocomplex the metal with an appropriate complexing agent such as citricacid, tartaric acid and succinic acid so as to form a metallic salt,before adding it to the Cu electroplating liquid.

Besides, the amount of the catalyst metal, or the dispersion density ofthat catalyst metal per unit area which is present at the surface of theCu wiring 2, necessary for starting the electroless plating describedlater differs depending on the material of the barrier film 7 to beformed. Therefore, the amount of the catalyst metal 10 a to be added tothe Cu electroplating liquid is not particularly limited, and may beappropriately set according to the material of the barrier film 7 to beformed.

One example of the composition of the Cu electroplating liquidcontaining the complexed Pd added thereto and one example of a set of Cuelectroplating conditions are given below. <Composition of CuElectroplating Liquid> Copper sulfate: 200 g/l to 250 g/l Palladiumsulfate: 10 mg/l to 1 g/l Ammonium citrate: 20 mg/l to 4 g/l (sodiumcitrate or the like may also be used) Sulfuric acid: 10 g/l to 50 g/lChloride ion: 20 mg/l to 80 mg/l Additive such as brightener:appropriate amount

<Cu Electroplating Conditions> Plating: 2.83 A Plating time: 4 min 30sec (1 μm) Plating liquid temperature: 25° C. to 30° C. Cathode currentdensity: 1 mA/cm² to 5 mA/cm²

In addition, while the Cu electroplating has been described as conductedin a copper sulfate bath in the foregoing, the Cu electroplating may beconducted by use of a copper borofluoride bath, a copper pyrophosphatebath, a copper cyanide bath or the like.

Next, as shown in FIG. 8, surplus portions of Cu 9, the barrier metalfilm 4 and the Cu seed layer 5 are removed, to leave Cu 9 only in thegroove 8, thereby forming the Cu wiring 2. As a result, Pd contained inthe Cu wiring 2 is exposed at the surface of the Cu wiring 2. That is,the catalyst metal 10 a for functioning as a catalyst in the formationof the barrier film 7 by electroless plating in the subsequent step isexposed at the surface of the Cu wiring 2.

Here, the technology generally applied to the removal of a surplusportion of Cu 9 is polishing by CMP. In this step, it is necessary tofinish the polishing at the surface of the inter-layer insulating film 3so as to leave the wiring material only in the groove 8, and, further,it is preferable to control the polishing so that the wiring materialwill not be left on the inter-layer insulating film 3. In the step ofpolishing by CMP, the plurality of materials of Cu 9, the barrier metal4 and the Cu seed layer 5 must be polished away, and it is thereforenecessary to control the polishing liquid (slurry), the polishingconditions and the like according to the materials to be polished. Forthis purpose, a plurality of polishing steps may be required in somecases. One example of a set of CMP conditions for the surplus Cu isgiven below. <CMP Conditions for Cu> Polishing pressure: 100 g/cm²Rotating speed: 30 rpm Rotary pad: laminate of nonwoven fabric andclosed-cell foam Slurry: H₂O₂ added (alumina-containing slurry) Flowrate: 100 cc/min Temperature: 25 to 30° C.

Next, the barrier film 7 is formed on the Cu wiring 2. In this case, ifrequired, a pretreatment for removing a spontaneous oxide film formed onthe Cu wiring 2 after the polishing step by CMP is applied, andthereafter the barrier film 7 is formed on the Cu wiring 2 as shown inFIG. 8 by an electroless plating process. With the electroless platingprocess adopted, the barrier 7 can be selectively formed only on the Cuwiring 2, whereby a step of etching the barrier film 7 can be omitted.One specific example of the pretreatment process is given below.

<Pretreatment>

(1) Degreasing treatment: The wettability of the surface is enhanced byalkali degreasing or acid degreasing.

(2) Acid treatment: Neutralization with 2 to 3% hydrochloric acid or thelike is conducted and, simultaneously oxidized Cu at the surface isremoved.

(3) Rinsing with Pure Water

In the above pretreatment, examples of the treating methods in (1)degreasing treatment, and (2) acid treatment include a spin treatment byuse of a spin coater, a paddle treatment (liquid paddling), and adipping treatment.

Next, a CoWP film, for example, is formed as the barrier film 7 on thesurface of the Cu wiring 2 by electroless plating. To form the CoWPfilm, as shown in FIG. 9, a CoWP electroless plating reaction is startedby using Pd, which is the catalyst metal 10 a, exposed at the surface ofthe Cu wiring 2 as a catalyst. Then, the electroless plating reaction iscontinued under an autocatalytic action, whereby the CoWP film can beformed on the Cu wiring 2 as shown in FIG. 10.

Here, as described above, Pd being the catalyst metal 10 a is exposedonly at the surface of the Cu wiring 2, and the electroless platingproceeds only where Pd is present. Therefore, the barrier 7 can beselectively formed only on the Cu wiring 2.

In addition, the barrier film 7 is not limited to the CoWP film in thepresent invention; the barrier film 7 may also be formed by anelectroless plating process using a cobalt alloy or a nickel alloy.Examples of the cobalt alloy include CoP, CoB, CoW, CoMo, CoWB, CoMoP,and CoMoB. Examples of the nickel alloy include NiWP, NiWB, NiMoP, andNiMoB. Further examples of the usable material include alloys containingboth Co and Ni, and alloys containing both W and Mo. An addition oftungsten or molybdenum to cobalt or nickel increases the copperdiffusion preventive effect. Also, phosphorus or boron auxiliarily addedin the electroless plating causes the formed film of cobalt or nickel tohave a fine crystal structure, thereby contributing to the copperdiffusion preventive effect.

One example of the composition of the electroless plating liquid for usein the above-mentioned electroless plating and one example of a set ofelectroless plating conditions are given below.

(In the case of CoP)<

Composition of Electroless Plating Liquid>

Cobalt chloride: 10 to 100 g/l (cobalt sulfate or the like)

Glycine: 2 to 50 g/l (ammonium salt of citric acid, tartaric acid,succinic acid, malic acid, malonic acid, formic acid or the like, or amixture thereof, or the like)

Ammonium hypophosphite: 2 to 200 g/l (formalin, glyoxylic acid,hydrazine, ammonium boron hydride, dimethylamineborane (DMAB), or thelike)

Ammonium hydroxide (tetramethylammonium hydroxide (TMAH) or the like: pHregulator) <Electroless Plating Conditions> Plating liquid temperature:50 to 95° C. pH of plating liquid: 7 to 12

When formalin, glyoxylic acid, hydrazine or the like is used in place ofammonium hypophosphite in the above electroless plating liquidcomposition, the resulting barrier film does not contain phosphorus (P).Besides, when dimethylamineborane (DMAB) or the like is used in place ofammonium boron hydride, the resulting film contains boron (B) in placeof phosphorus (P). This applies also to the following electrolessplating liquid composition. (In the cases of CoWP, CoMoP, NIWP, andNiMoP)

Composition of Electroless Plating Liquid

Cobalt chloride or nickel chloride: 10 to 100 g/l (cobalt sulfate,nickel sulfate or the like)

Glycine: 2 to 50 g/l (ammonium salt of citric acid, tartaric acid,succinic acid, malic acid, malonic acid, formic acid or the like, or amixture thereof, or the like)

Ammonium hypophosphite: 2 to 200 g/l (formalin, glyoxylic acid,hydrazine, ammonium boron hydride, dimethylamineborane (DMAB), or thelike)

Ammonium hydroxide (tetremethylammonium hydroxide (TMAH) or the like: pHregulator) <Electroless Plating Conditions> Plating liquid temperature:50 to 95° C. pH of plating liquid: 8 to 12

In the above electroless plating, like in the pretreatment, a film canbe formed by a spin treatment using a spin coater, a paddle treating, adipping treatment or the like.

By the above procedure it is possible to manufacture a high-qualitysemiconductor device, as shown in FIG. 1, which has an excellentelectro-migration resistance together with a copper diffusion preventivefunction and in which RC delay is suppressed.

As has been described above, in the method of manufacturing asemiconductor device according to the present invention, the catalystmetal 10 a is preliminarily contained in the metallic wiring, at thetime of forming the Cu wiring 2. Specifically, in forming the Cu wiring2 filling the groove by electroplating, the catalyst metal 10 a is addedto the electroplating liquid, and the Cu wiring 2 filling the groove isformed by electroplating using the electroplating liquid. Then, of thecatalyst metal 10 a contained in the Cu wiring 2, the catalyst metal 10a present at the surface of the Cu wiring 2 is used as nuclei ofcatalyst, namely, as a catalyst for starting an electroless platingreaction, and, under this condition, electroless plating is conducted tothereby form the barrier film 7 having the copper diffusion preventivefunction on the Cu wiring 2.

With the Cu wiring 2 formed by such a method, the catalyst metal 10 a tobe the catalyst for starting the electroless plating reaction isdispersed inside the Cu wiring 2 and at the surface of the Cu wiring 2,so that the formation of the Cu wiring 2 provides the same effect asthat in the case of conducting a catalytically activating treatment inthe conventional manufacturing method, and the catalytically activatingtreatment step indispensable to the conventional manufacturing method isunnecessitated. As a result, in the method of manufacturing asemiconductor device according to the present invention, it is possibleto efficiently form the barrier film 7 by simplified manufacturingsteps, and to manufacture a high-quality semiconductor device in whichthe diffusion of copper atoms into the inter-layer insulating film issecurely prevented.

Besides, in the method of manufacturing a semiconductor device accordingto the present invention, the catalytically activating step is notconducted as above-described, so that the Cu wiring 2 is not etched atthe time of forming the barrier film 7. Therefore, the problems whichwould cause malfunctions of the semiconductor device, such as a rise inwiring resistance and a worsening of electro-migration resistance due toetching of the Cu wiring 2, are obviated, and a high-qualitysemiconductor device can be manufactured.

Furthermore, since the catalytically activating step is not conducted inthe method of manufacturing a semiconductor device according to thepresent invention, the adsorption or remaining of the catalyst metalonto the inter-layer insulating film 3 as in the conventionalmanufacturing method is obviated. As a result, formation of the barrierfilm 7 on the inter-layer insulating film is prevented, so that it ispossible to enhance the selectivity of film formation at the time offorming the barrier film 7, and to manufacture a high-qualitysemiconductor device.

Incidentally, the above-described method of manufacturing asemiconductor device is applicable to both a groove wiring technologybased on the Damascene process and a groove wiring technology based onthe dual Damascene process.

Now, a specific manufacturing method based on the so-called dualDamascene process, in which the present invention is applied to asemiconductor device having a multilayer wiring, will be describedbelow.

First, in the same manner as in the case of the monolayer wiringdescribed above, a first wiring, namely, a lower-layer wiring as shownin FIG. 11 is formed. Next, a second wiring, namely, an upper-layerwiring is formed according to the following procedure. In the followingdescription, the same members as those in the above description aredenoted by the same symbols as used above, and detailed descriptionthereof is omitted.

To form the upper-layer wiring, first, a hydrofluoric acid (HF) solutiontreatment for the purpose of removing the copper atoms remaining on aninter-layer insulating film 3 is conducted.

Next, as shown in FIG. 12, an inter-layer insulating film 10 bconsisting of SiOC corresponding to the depth of a via hole and an SiNfilm 11 for a copper diffusion preventive purpose are sequentiallyformed by a CVD process.

Subsequently, as shown in FIG. 13, the SiN film 11 is processed byphotolithography followed by dry etching, to form an opening 12 in apattern at a position which is directly above a lower-layer wiring 2 andwhich corresponds to the via hole.

Next, as shown in FIG. 14, SiOC is built up on the SiN film 11 inclusiveof the opening 12 in an amount corresponding to the depth of anupper-layer wiring by a CVD process, to form an inter-layer insulatingfilm 13.

Subsequently, a resist is applied to the inter-layer insulating film 13,and resist mask (omitted in the figure) is formed by photolithographytechnique. Thereafter, the inter-layer insulating film 13 is processedby etching using the resist mask. The etching is made to proceedfurther, thereby processing the inter-layer insulating film 10 b asshown in FIG. 15. This etching is stopped on the barrier film 7.

Next, a pattern of a resist (omitted in the figure) is again formed onportions other than the portion corresponding to the wiring shape byphotolithography technique. Then, etching is conducted by use of theresist mask. When the resist is removed, as shown in FIG. 16, a via hole15 communicated to the barrier film 7 and having the inter-layerinsulating film 10 b as side walls is formed in the inter-layerinsulating film 10 b, and an upper-layer wiring groove 14 having theinter-layer insulating film 13 and the SiN film 11 as side walls isformed in the inter-layer insulating film 13. Hereinafter the wiringgroove 14 and the via hole 15 will be collectively referred to a recess16.

Subsequently, as shown in FIG. 17, a barrier metal film 17 consisting,for example, of TaN for preventing the diffusion of copper into theinter-layer insulating film 10 b and the inter-layer insulating film 13is formed by a PVD process, followed by formation of a Cu seed layer 18by a PVD process. The material of the barrier metal film 17 is notlimited to TaN; materials excellent in barrier property against Cu, suchas Ta, TiN, and WN can be used. The Cu seed layer 18 serves as aconductive layer at the time of forming a film of Cu by electroplatingin the subsequent Cu filling step. The method for forming the barriermetal film 17 and the Cu seed layer 18 is not limited to the PVDprocess; they may be formed by a CVD process. The film thicknessesdepend on design rules, but it is preferable that the film thickness ofthe barrier film 17 is not more than 50 nm, and the film thickness ofthe Cu seed layer 18 is not more than 200 nm.

Next, as shown in FIG. 18, Cu electroplating is conducted to fill therecess 16 with Cu 19. In this case, in the same manner as describedabove, Pd as a catalyst metal 20 is preliminarily added to a Cuelectroplating liquid used for the Cu electroplating. The catalyst metal20 functions as a catalyst for starting an electroless plating reactionat the time of forming a barrier film 22 which will be described later.The film thickness of Cu 19 differs depending on the depth of the recess16, but it is preferably not more than 2 μm by a standard.

Subsequently, as shown in FIG. 19, surplus portions of Cu 19, thebarrier metal film 17 and the Cu seed layer 18 are removed, leaving Cu19 only in the recess 16, to form a Cu wiring 21 which is an upper-layerwiring. As a result, Pd contained in the Cu wiring 21 is exposed at thesurface of the Cu wiring 21. Namely, the catalyst metal 20 whichfunctions as a catalyst at the time of forming the barrier film 22 inthe subsequent step is exposed at the surface of the Cu wiring 21.

For removal of surplus Cu 19, polishing by CMP in general use can beused. In this step, it is necessary to finish the polishing at thesurface of the inter-layer insulating film 13 so as to leave Cu 19 as awiring material only in the recess 16, and, further, it is preferable tocontrol the polishing so that the wiring material is not left on theinter-layer insulating film 13. In the polishing step by CMP, theplurality of materials of Cu 19, the barrier metal film 17 and the Cuseed layer 18 must be polished away, so that it is necessary to controlthe polishing liquid (slurry), the polishing conditions and the likeaccording to the materials to be polished. Therefore, a plurality ofpolishing steps may be needed in some cases.

Next, the barrier film 22 is formed on the Cu wiring 21. In this case,as required, a pretreatment for removing a spontaneous oxide film formedon the Cu wiring 21 after the polishing step by CMP is conducted, andthereafter the barrier film 22 is formed on the Cu wiring 21 by anelectroless plating process. With the electroless plating processadopted, the barrier film 22 can be selectively formed only on the Cuwiring 21, so that a step of etching the barrier film 22 can be omitted.A specific example of the pretreatment process is given below.

<Pretreatment>

(1) Degreasing treatment: The wettability of the surface is enhanced byalkali degreasing or acid degreasing.

(2) Acid treatment: Neutralization with 2 to 3% hydrochloric acid or thelike is conducted and, simultaneously, oxidized Cu at the surface isremoved.

(3) Rinsing with Pure Water

Examples of the treating method in (1) degreasing treatment, and (2)acid treatment in the above-mentioned pretreatment include a spintreatment using a spin coater, a paddle treatment (liquid paddling), anda dipping treatment.

Subsequently, a CoWP film, for example, as the barrier film 22 is formedon the surface of the Cu wiring 21 by electroless plating. To form theCoWP film, a CoWP electroless plating reaction is started by using Pd,which is the catalyst metal 20, exposed at the surface of the Cu wiring21 as a catalyst. Then, the electroless plating reaction is allowed toproceed under an autocatalytic action, whereby the CoWP film as thebarrier film 22 can be formed on the Cu wiring 21 as shown in FIG. 20.

Here, as has been described above, Pd as the catalyst metal 20 isexposed only at the surface of the Cu wiring 21, and the electrolessplating proceeds only where Pd is present. Therefore, it is possible toselectively form the barrier film 22 only on the Cu wiring 21.

Followingly, the same or similar process is repeated, whereby it ispossible to produce a Cu multilayer wiring in which diffusion of copperis securely prevented and which is high in reliability.

While examples of the cases where the present invention is applied to amonolayer wiring and to a multilayer wiring have been described in theforegoing, the present invention is not limited to the abovedescriptions, and appropriate modifications are possible withoutdeparting from the gist of the present invention.

In addition, in forming a wiring in a multilayer structure, theformation of the wiring is not limited to the formation of the wiring bythe dual Damascene process, and any method or process may be adopted.

INDUSTRIAL APPLICABILITY

The method of manufacturing a semiconductor device according to thepresent invention is a method of manufacturing a semiconductor deviceincluding a barrier film having a copper diffusion preventive functionand formed on a copper-containing metallic wiring, the method includingthe steps of: conducting electroplating by use of an electroplatingliquid containing a catalyst metal added thereto so as thereby to formthe metallic wiring containing the catalyst metal; and conductingelectroless plating by use of the catalyst metal exposed at the surfaceof the metallic wiring as a catalyst so as thereby to form the barrierfilm having the copper diffusion preventive function on the metallicwiring.

In the method of manufacturing a semiconductor device according to thepresent invention as above-mentioned, the formation of the metallicwiring by the electroplating using the electroplating liquid containingthe catalyst metal added thereto produces the same effect as that in thecase of conducting a catalytically activating treatment in theconventional manufacturing method. In the present invention, therefore,the catalytically activating treatment step indispensable to theconventional manufacturing method is not necessitated, so that it ispossible to efficiently form the barrier film by simplifiedmanufacturing steps, and to manufacture at low cost a high-qualitysemiconductor device in which the diffusion of copper atoms into theinter-layer insulating film is securely prevented.

Besides, in the method of manufacturing a semiconductor device accordingto the present invention, the absence of the catalytically activatingstep ensures that the metallic wiring itself is not etched, and theproblems which would cause malfunctions of the semiconductor device,such as a rise in wiring resistance and a worsening of electro-migrationresistance due to etching of the metallic wiring, are obviated, so thatit is possible to manufacture a high-quality semiconductor device.

Furthermore, since the catalytically activating step is not conducted inthe method of manufacturing a semiconductor device according to thepresent invention, the adsorption or remaining of the catalyst metalonto the inter-layer insulating film as in the conventionalmanufacturing method is obviated, so that it is possible to enhance theselectivity of film formation at the time of forming the barrier film,and to manufacture a high-quality semiconductor device.

According to the present invention, therefore, it is possible to providea semiconductor device which is suitable for enhancing the operatingspeed thereof and which is high in quality and reliability.

1. A method of manufacturing a semiconductor device comprising a barrierfilm having a copper diffusion preventive function and formed on acopper-containing metallic wiring, said method comprising the steps of:conducting electroplating by use of an electroplating liquid containinga catalyst metal added thereto so as thereby to form said metallicwiring containing said catalyst metal; and conducting electrolessplating by use of said catalyst exposed at the surface of said metallicwiring as a catalyst so as thereby to form said barrier film having saidcopper diffusion preventive function on said metallic wiring.
 2. Themethod of manufacturing a semiconductor device according to claim 1,wherein said catalyst metal is added to said electroplating liquid in acomplexed form.
 3. The method of manufacturing a semiconductor deviceaccording to claim 1, wherein said catalyst metal is one selected fromthe group consisting of Au, Pt, Pd, Ag, Ni, and Co.
 4. The method ofmanufacturing a semiconductor device according to claim 1, wherein saidbarrier film is comprised of a cobalt alloy or a nickel alloy.